Jiangli Zhu

 

 

 

 

PhD Student in

Computer Engineering

 

Dept. of EECS
Glennan 519A
Case Western Reserve Univ.
Cleveland, OH 44106 USA

 

Phone: (+1) 216-235-8646
E-mail: Jiangli.Zhu@case.edu 

Lab_Jan09

 

Biography

 

I was born in Changzhou, Jiangsu, China, in 1982. I received the BS and MS degrees in Electrical Engineering from Zhejiang University (ZJU), Hangzhou, China, in 2004 and 2006, respectively. I am currently a Ph.D. student in the EECS department, Case Western Reserve University. I am working with Prof. Xinmiao Zhang and my main research focus is on VLSI architecture design.

 

Research Interests

 

1.    VLSI architecture design for error-correcting coding

2.    VLSI design for digital signal processing

3.    Low power VLSI design

 

For more details, please visit our lab homepage: VLSI System Architecture Laboratory

Journal Publications

 

1.      J. Zhu and X. Zhang, "Efficient VLSI architecture for soft-decision decoding of Reed-Solomon codes," IEEE Trans. on Circuits and Systems - I, vol. 55, no. 10, pp. 3050-3062, Nov. 2008.

2.      J. Zhu, X. Zhang, and Z. Wang, "Backward interpolation architecture for algebraic soft-decision Reed-Solomon decoding," IEEE Trans. on VLSI Systems, vol. 17, no. 11, pp. 1602-1615, Nov. 2009.

3.      X. Zhang and J. Zhu, "High-throughput interpolation architecture for Algebraic soft-decision Reed-Solomon decoding," To appear in IEEE Trans. on Circuits and Systems - I.

Conference Publications

 

1.      X. Zhang and J. Zhu, "Low-complexity interpolation architecture for soft-decision Reed-Solomon decoding," Proc. of ISCAS, New Orleans, LA, May 2007.

2.      J. Zhu and X. Zhang, "Efficient interpolation architecture for soft-decision Reed-Solomon decoding," Proc. of SiPS, Shanghai, China, Oct. 2007.

3.      J. Zhu, X. Zhang, and Z. Wang, "Novel interpolation architecture for low-complexity chase soft-decision decoding of Reed-Solomon codes," Proc. of ISCAS, Seattle, WA, May 2008.

4.      X. Zhang, and J. Zhu, "Efficient interpolation architecture for soft-decision Reed-Solomon decoding by applying slow-down," Proc. of SiPS, Washington D. C., Oct. 2008

5.      J. Zhu, and X. Zhang, "Scalable interpolation architecture for soft-decision Reed-Solomon decoding," Proc. of APCCAS, Macao, China, Nov. 2008.

6.      J. Zhu, X. Zhang, and Z. Wang, "Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes," Proc. of ICCD, Lake Tahoe, CA, Oct. 2008.

7.      J. Zhu, and X. Zhang, "Factorization-free low-complexity Chase soft-decision decoding of Reed-Solomon codes," Proc. of ISCAS, Taipei, May 2009.

8.      X. Zhang and J. Zhu, "Interpolation-based hard-decision Reed-Solomon decoders," Proc. of ISIC, Singapore, Dec 2009.

9.      J. Zhu and X. Zhang, "Efficient generalized minimum-distance decoder of Reed-Solomon codes," Proc. of ICASSP, Dallas, TX, Mar. 2010.

10.  J. Zhu and X. Zhang, "High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding," Proc. of ISCAS, Paris, France, May 2010.

Scholarship

 

Chinese Student Award, Dept. of EECS, Case Western Reserve University, 2008

Capabilities & Skills

 

Programming:

Verilog HDL, C/C++, Java, Perl

 

EDA Tools:

Mentor Modelsim, Synopsys Design Complier, Synopsys CCSS, Cadence SPW

EDA Tools

 

Place and Route with SOC Encounter

Tutorial for VHDL Simulation with QuickHDL and QHPro

VLSI for Communications Related Research Group

 

VLSI Signal Processing at UMN

Rensselaer VLSI System Architecture Laboratory

VLSI Signal Processing at Rice University

DSP Lab at UMD

On-Line Source

 

IEEE Xplore

IEEE TVLSI

IEEE TCAS I

ACM

Friends

 

Bin Guo (IIT)

Yingxian Wu (PSU)

Yanfei Zhu (OSU)

Chaoyang Ma (Leeds, UK)

Bainan Chen (CWRU)

Hongkun Li (IIT)

Sha Yao (KTH)

Bin Zhou (VT)

Junda Zhu (OSU)

Ji Bo (OSU)

Jia Yu (UC-Berkeley)

Meng Sun (Buffalo)

Zhenming Zhou (UFL)

Xinye Lou (Rochester)

Xie Lin (UWM)

 

Yu Zhou (CWRU)

Shan Chu (SUNY)

 

 

Favorites

 

Formula1

Weiqi

Soccer

Swimming

 

Last Updated: Jan. 28, 2010