NAME

power3 - supply-gating logic synthesis tool

SYNOPSIS

power3 [name=value] ... 

DESCRIPTION

Power3 is the third version of the supply-gating logic synthesis tool developed at C.W.R.U. in 2006. General logic synthesis is performed by SIS which must be available as an executable.  SIS 1.3 is preferred.

Power3 reads from standard input a logic description file in blif format and produces by default on standard output a circuit description in SPICE format. The mode option (see below) determines the output generated. SPICE output makes reference to header.sp (or other filename under the control the header option) and files of the form input/i#.sp where # is a decimal number, for each circuit input. The header file must contain voltage sources, power measurement commands and the gate library.

Power3 accepts program options from the command line or from UNIX environment variables.  Options on the command line take precedence over environment variables. The values used by the program are reported in the output (as SPICE comment lines).

The following options are interpreted by power3: 

aratio

The maximum ratio of modified to original area due to supply-gating a partition. The modified circuit is used only if the value is not exceeded. If no aratio value is specified, 1.5 is used. Although scaled for length, the relative area of gate types is hard-coded in the program.

ctrl

If non-negative, selects a partition's input variable by position (counting from zero) as the control variable. Used in testing to defeat control variable ranking. If no ctrl value is specified, -1 is used.

depth

The maximum depth of recursion of Shannon decomposition. Shannonization is performed recursively on each of the two cofactors and on the shared logic. A depth value of 1 defeats the recursion feature. If no depth value is specified, 2 is used.

header

Filename of header file referenced in the output. The file is not read. This feature allows specific header files to be associated with the output when it is generated. For example, a study of 32 nm vs. 70 nm technology might specify "len=32 header=header32.sp" in one run and "len=70 header70.sp" in another. The header files would contain technology node-specific details to be included for the SPICE runs. If no header value is specified, header.sp is used.

initmap

Perform the initial technology mapping if the initmap value is non-zero.  The input circuit is technology mapped to producing the "original" circuit used for comparison with the modified circuit. This ensures that the comparison is not dependent on the quality of the synthesis of the input circuit, but if the circuit is very large, SIS will hang so the initial mapping must be avoided. If no initmap value is specified, 1 is used.

kvpe

The number of vertices that cost the same as one edge. The kvpe value is used in the hyperedge cost function which weighs the cost of hyperedges relative to the optimal number of vertices in a partition. If no kvpe value is specified, 10 is used.

len

The technology scale in nanometers. Used to estimate area and power to limit the size of the circuit due to Shannonization. If no len value is specified, 32 is used.

max

Maximum number of candidates circuits on which to try full technology mapping. Each input variable is tried as a control variable, setting it to zero and one, and removing trivialized gates. The circuits with the least numbers of gates are candidates. If no max value is specified, three candidates are fully mapped.

mode

Bitmap of output to generate.  All output is given with program options. Mode 0x002-0x040 output is given for each partition. Mode 0x100-0x400 output is given with partition statistics. Circuits are given in blif format except as noted. If no mode value is specified, 0x100 is used.

0x001		The original circuit
0x002		Number of gates in cofactors with the each input as control variable
0x004		Control variables used on each Shannonized circuit
0x008		Cofactored circuits (without shared logic extracted)
0x010		Shared logic circuit after extraction
0x020		Two cofactor and shared logic circutis after extraction and separation
0x040		Two cofactor and shared logic circuits after final synthesis
0x080		Final circuit in heirarchical, diagnostic format
0x100		Original and final circuits in SPICE format with execution time report
0x200		Original and final circuits in Verilog format
0x400		Partitioned circuit in Verilog format

pmos

Perform the discredited pmos gating technique if the pmos value is non-zero. This technique uses one pmos transistor for all of a cofactor's output, cross-coupling the logic circuits. This feature needs to be redesigned to generate one pmos transistor per output. If no pmos value is specified, 0 is used. 

pratio

The maximum ratio of modified to original estimated power due to supply-gating a partition. The modified circuit is used only if the value is not exceeded. Power is estimated as area but halved for gates in the cofactors. If no pratio value is specified, 1.5 is used. Although scaled for length, the relative area of gate types is hard-coded in the program. 

seed

The random number seed. The Monte Carlo technique employed for partitioning requires random numbers. If no seed value is specified, the program seeds the random number generator with the time of day, which causes program results to vary for each run. To get repeatable results, set the seed value explicitly.

sis0

Filename of SIS input. Before sending data to SIS, it is copied to a file.  Used in testing to trace data sent to SIS. If no sis0 value is specified, SIS input is not copied to a file.

sis1

Filename of SIS output. After receiving data from SIS, it is copied to a file.  Used in testing to trace data received from SIS. If no sis1 value is specified, SIS output is not copied to a file.

siscofactor

SIS command used on each cofactor to remove trivial gates.

siscontrol

SIS command used in the first round of selection of the control variable, with each input as the control variable for the partition. 

sisfinal

SIS command for the final technology mapping, the last synthesis on a partition.  Also used in the second round of selection of the control variable, on the candidate circuits. 

sisshared

SIS command used to find shared logic among the two cofactors. 

tries

The number of iterations of the uncoarsening algorithm per vopt, at each level of uncoarsening.  In each iteration, a vertex is selected at random and tried in each partition. This limits the duration of the partitioning algorithm. If no tries value is specified, 10,000 is used.

vopt

The optimal number of vertices per partition. Used in the vertex and hyperedge cost functions.  Also used to determine the number of iterations of the uncoarsening algorithm. If no vopt value is given, 25 is used. If value is zero, partitioning is defeated so all vertices are placed in a single partition.

FILES

	sis		SIS 1.3 executable file
	gatelib.genlib		SIS Genlib file for gate library

SEE ALSO

L. Leinweber and S. Bhunia, "Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction," DATE, 2008

L. Leinweber, "Fine-Grained Supply Gating for Low Dynamic and Leakage Power Using Hypergraph Paritioning and Shannon Decomposition, Master's Thesis (S. Bhunia, Advisor), Case Western Reserve University, 2007

S. Bhunia, N. Banerjee, Q. Chen, H.Mahmoodi, K. Roy. "A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating," Proceedings of the Design Automation Conference, 2005.

E.M. Sentovich, et al., SIS: A System for Sequential Circuit Synthesis, Memorandum No. UCB/ERL M92/41, University of California, Berkeley, 1992.