NanoScape Lab
Architecture, Circuit and Model for Nanocomputing
Welcome to the Homepage of Nanoscape Research Laboratory!
Overview of Current Research
Current research at Nanoscape has four main thrusts:
1. Adaptive Nanocomputing
While
emerging nanodevices show promises in terms of terascale integration,
ultra low-power operation or tera-hertz switching, system design with
these devices involves some major challenges. At nanometer scale, these
devices suffer from high defect rate and susceptibility to large
parameter variations. We target developing model, architecture and
circuit for adaptive nanocomputing, which address these challenges and
fit to the dense and regular structure of the nano-fabric. Application
of these techniques is also being investigated to a specific carbon
nanotube based Nano-Electromechanical System (NEMS) complementary
Switch (in collaboration with Prof.
Massood
Tabib-Azar at Case) as well as to a poly-SiC based NEMS switch
suitable
for high-temperature electronics (in collaboration with Prof. Mehran
Mehregany at Case).
2. Low Power and Robust System Design
Power and
robustness of operation have emerged as two major concerns for digital
design with nanoscaled CMOS. Low power design techniques such as
voltage scaling, dual-Vth, power gating typically impose contradictory
design requirements with respect to robustness of a design.
Nanoscape targets developing design methodology for low power and
variation tolerance, while minimizing the design overhead. Of
particular importance is tolerance to process-induced parameter
variations as well as to time-dependent device degradations (in
collaboration with Prof. Kaushik Roy
at Purdue University and Prof.
Saibal Mukhopadhyay at Georgia Tech).
3. Hardware Security and Trust
Hardware Intellectual Property (IP) piracy and reverse engineering efforts have emerged as major concerns for IP vendors and design houses. It has been critical develop low-cost design techniques for preventing IP infringement at different stages of IP life-cycle. Nanoscape is presently investigating netlist and register transfer level design solutions for hardware IP protection that ensures trust and security for all parties involved in system design flow while not affecting end user experience. Another major security concern for hardware is malicious alteration of a design in an untrusted foundry. Conventional test generation, application and coverage determination do not directly apply to detect such alterations, commonly referred as hardware Trojan. We are exploring novel solutions for post-silicon Trojan detection techniques as well as design methodology to facilitate Trojan detection.
4. Nanoelectronics for Bio-Implantable Devices
For centuries, researchers and scientists around the globe have dreamed of understanding central nervous system and performing surgical interventions to manipulate its activity. With the advances in bio-MEMS and nanoelectronics, interpreting and engineering the activity of the central nervous system in terms of its communication with body parts are poised to make dramatic progress using miniaturized implantable biomedical microsystems. Such implantable microsystems require monitoring the activities of neural network at cellular level using arrays of micro-electrodes. In Nanoscape, research efforts are underway to develop efficient algorithms and hardware design techniques for performing spike detection, alignment and classification of the action potential signals from a large number of electrodes in an efficient manner (in collaboration with Prof. Hillel Chiel, Prof. Steve Garverick and Prof. Massood Tabib-Azar at Case).
Last Update Dec 22, 2008